1. Field of Invention
The present invention is related to semiconductor and in particular to flash memories and the conditions to erase a flash memory cell.
2. Description of Related Art
In a conventional erase condition for flash memory cells a high voltage is applied from the source to the gate of the cell. To accomplish the erasure of the cell, to avoid breakdown of the word line decoder and to perform the erasure at a reasonable rate, a high negative voltage is applied to the gate of the cell while a moderately high positive voltage greater in amplitude than the chip bias voltage is applied to the source. This requires that both a positive pump circuit and a negative pump circuit exist on the flash memory chip. There are several problems that must be handled when two pump circuits of opposite polarity are on the same chip. Besides increase in chip power considerable protection circuitry and guarding methodology are required to isolate the pump circuitry and avoid device breakdown.
In U.S. Pat. No. 5,485,423 (Tang et al.) discloses a conventional erase condition for a selected flash memory cell. In order to erase the selected cell, a high negative voltage of about -8.5V is applied to the gate, G, while a high positive voltage of about +5V is applied to the source, S, as shown in FIG. 1a. The drain, D, is left floating and the semiconductor bulk, B, is connected to ground. The high negative gate voltage and the high positive source voltages requires that two voltage pump circuits be contained on the flash memory chip to supply these voltages. The thirteen volts between the source and the gate produce a sufficient voltage to invoke Fowler-Nordheim tunneling and to erase the cell at an appropriate speed. In FIG. 1b of prior art is shown the voltages of prior art necessary to deselect the cell and prevent erase disturb conditions. As shown in FIG. 1b, zero volts are applied to the gate, G, the source, S, and the semiconductor bulk, B, with the drain, D, left floating.
In U.S. Pat. No. 5,438,542 (Atsumi et al.) a flash memory cell is formed on a P-type substrate with the bias conditions for erase shown in FIG. 2. The gate voltage is -V.sub.C and V.sub.A applied to the semiconductor substrate, V.sub.A +V.sub.B applied to the source and the drain floating. This bias configuration requires two voltage pump circuits, one for -V.sub.C and one for V.sub.A +V.sub.B. The requirement for a chip to have for two pump circuits of opposite voltage creates a number of problems with which the design of the chip must take into consideration including isolation and avoid device break down. The extra power dissipation need to support two pump circuits is also a limitation.